I am torn on this chip. One way of looking at it is negative as they are adding custom instructions that are not part of the RISC-V standard. Part of me hates the fragmentation.

On the other hand, the alternative is that they release another MIPS chip ( MIPS ISA, not RISC-V ). That obviously fragments the CPU space even more and does nothing to drive the RISC-V space forward.

If I take a step back, this is exactly the freedom that RISC-V represents. Not only did it make sense for MIPS to adopt RISC-V over their own ISA but this is the kind of thing that would not be possible if they went with ARM.

What makes RISC-V better than ARM is the freedom, not the lack of licensing fees. I think this is an example of how RISC-V wins in the end.

Equivalent instructions will make it into the RISC-V spec ( official extensions ) and future MIPS chips will no doubt use the standard at some point.

In the end, this just creates more demand for and more support for RISC-V on Linux and Open Source RISC-V toolchains ( such as compilers ).

Anything that moves RISC-V forward is positive.